Integrated circuits (IC) are at the core of almost all modern digital systems. As the use of semiconductor devices becomes more prevalent, more and more requirements are placed on a chip. The challenge is therefore to fit more processing power into a single IC package to accommodate customer demands.
This challenge has been met by making devices smaller and smaller. In other words, devices are becoming smaller even as their processing power increases. This has inevitably created a number of opportunities related to the packaging of these components. Among the more common problems in IC packaging is package warpage due to coefficient of thermal expansion (CTE) mismatches and poor adhesion between the lid and the body of a package. It has also become increasingly challenging to fit more decoupling capacitors into a single IC package as the need for power increases.
Thus, it is highly desirable to have a mechanically stable packaged device that has enough space for all the decoupling capacitors to be placed on the package substrate while maintaining the overall size of the IC package. In short, an IC package needs to be able to hold all the different components to accommodate the ever-increasing need for more processing power without sacrificing area or performance.